UNIT 1 INTEL
8085 ARCHITECTURE 9
Introduction to 8085: 8085 architecture- Instruction Set - Assembler
Directives- Assembly Language-Programming with 8085.
UNIT 2 INTEL
8086/8088 ARCHITECTURE 9
Introduction to 8086/8088: 8086/8088 architecture- Instruction Set- Assembler
Directives- Assembly Language Programming with 8086/8088- Special Architectural
Features.
UNIT 3 COMMUNICATION INTERFACES 9
Basic Peripherals & their interfacing with
8086/8088: Semiconductor
Memory Interfacing- Dynamic RAM Interfacing- Interfacing I/O Ports- PIO 8255; Modes
of Operation.
UNIT 4
PERIPHERAL INTERFACES
9
Special
Purpose Programmable Peripheral Devices & their Interfacing:
Programmable Interval Timer 8253- Programmable Interrupt Controller 8259A. DMA Controller 8257: DMA Transfers
& Operations.
UNIT
5
MULTIPROCESSOR SYSTEMS
9
Interconnection Topologies-
Software Aspects of Multiprocessor Systems- Numeric Processor 8087- Bus
Arbitration & Control- Tightly Coupled & Loosely Coupled Systems.
NOW START WID UNIT 1:-
8085:-
8085 pin
diagram
|
_________
_________
|
|
_|
\__/
|_
|
|
--> X1 |_|1
40|_|
Vcc (+5V) |
|
_|
|_
|
|
--> X2
|_|2
39|_| HOLD <-- |
|
_|
|_
|
|
<-- RESET OUT |_|3
38|_|
HLDA --> |
|
_|
|_
|
|
<-- SOD
|_|4
37|_| CLK (OUT) --> |
|
_|
|_ ________ |
|
--> SID
|_|5
36|_| RESET IN <-- |
|
_|
|_
|
|
--> TRAP
|_|6
35|_| READY <-- |
|
_|
|_
_ |
|
--> RST 7.5
|_|7
34|_| IO/M --> |
|
_|
|_
|
|
--> RST 6.5
|_|8
33|_| S1 --> |
|
_|
|_ __
|
|
--> RST 5.5
|_|9
32|_| RD --> |
|
_|
|_
__
|
|
--> INTR |_|10
8085A 31|_| WR
--> |
|
____
_|
|_
|
|
<-- INTA
|_|11
30|_| ALE --> |
|
_|
|_
|
|
<--> AD0
|_|12
29|_| S0 --> |
|
_|
|_
|
|
<--> AD1
|_|13
28|_| A15 --> |
|
_|
|_
|
|
<--> AD2
|_|14
27|_| A14 --> |
|
_|
|_
|
|
<--> AD3
|_|15
26|_| A13 --> |
|
_|
|_
|
|
<--> AD4
|_|16
25|_| A12 --> |
|
_|
|_
|
|
<--> AD5
|_|17
24|_| A11 --> |
|
_|
|_
|
|
<--> AD6
|_|18
23|_| A10 --> |
|
_|
|_
|
|
<--> AD7
|_|19
22|_| A9 --> |
|
_|
|_
|
|
(Gnd) Vss
|_|20
21|_| A8 --> |
|
|______________________|
|
|
|
|
|
|--------------------------------------------------------------|
Instruction set
•
ISA includes the information needed to interact with the
microprocessor.
•
Does not include information as to how microprocessor is
designed or implemented
•
Includes microprocessor instruction set, which would be the set
of all assembly languages instructions.
•
Also includes the complete set of accessible registers.
Arithmetic Group:
The arithmetic instructions add, subtract,
increment, or decrement data in registers or memory.
ADD
Add to Accumulator
ADI
Add Immediate Data to Accumulator
ADC
Add to Accumulator Using Carry Flag
ACI
Add Immediate data to Accumulator Using Carry
SUB
Subtract from Accumulator
SUI
Subtract Immediate Data from Accumulator
SBB
Subtract from Accumulator Using Borrow (Carry) Flag
SBI
Subtract Immediate from Accumulator Using Borrow (Carry) Flag
INR
Increment Specified Byte by One
DCR
Decrement Specified Byte by One
INX
Increment Register Pair by One
DCX
Decrement Register Pair by One
Logical
Group:
This group
performs logical (Boolean) operations on data in registers and memory and on
condition flags.
The logical AND, OR, and
Exclusive OR instructions enable you to set specific bits in the accumulator ON
or OFF.
ANA
Logical AND with Accumulator
ANI
Logical AND with Accumulator Using Immediate Data
ORA
Logical OR with Accumulator
OR
Logical OR with Accumulator Using Immediate Data
XRA
Exclusive Logical OR with Accumulator
XRI
Exclusive OR Using Immediate Data
Branch
Group:
The
branching instructions alter normal sequential program flow, either
unconditionally or conditionally. The unconditional branching instructions are
as follows:
JMP
Jump
CALL
Call
RET
Return
Conditional
branching instructions examine the status of one of four condition flags to
determine whether the specified branch is to be executed. The conditions that
may be specified are as follows:
NZ
Not Zero (Z = 0)
Z
Zero (Z = 1)
NC
No Carry (C = 0)
C
Carry (C=1)
PO
Parity Odd (P=0)
PE
Parity Even (P=1)
P
Plus (S=0)
M
Minus (S = 1)
INSTRUCTION SET
§ISA includes the information needed to
interact with the microprocessor.
§Does not include information as to how
microprocessor is designed or implemented
§Includes microprocessor instruction set, which
would be the set of all assembly languages instructions.
§Also includes the complete set of accessible
registers.
Q.
what is instruction sets ?
ISA
includes the information needed to interact with the microprocessor.
Does not
include information as to how microprocessor is designed or implemented
Includes
microprocessor instruction set, which would be the set of all assembly
languages instructions.Also includes the complete set of accessible registers.
Q. WHAT ARE THE TYPE OF INSTRUCTIONS
SETS?
Arithmetic Group:
The arithmetic instructions add, subtract, increment,
or decrement data in registers or memory.
ADD Add to
Accumulator
ADI Add
Immediate Data to Accumulator
ADC Add to
Accumulator Using Carry Flag
Arithmetic Group:
The arithmetic instructions add, subtract, increment,
or decrement data in registers or memory.
ADD Add to
Accumulator
ADI Add
Immediate Data to Accumulator
ADC Add to
Accumulator Using Carry Flag
ACI
Add Immediate data to Accumulator Using Carry
SUB
Subtract from Accumulator
SUI Subtract
Immediate Data from Accumulator
SBB Subtract
from Accumulator Using Borrow (Carry) Flag
SBI Subtract
Immediate from Accumulator Using Borrow (Carry) Flag
INR
Increment Specified Byte by One
DCR
Decrement Specified Byte by One
INX
Increment Register Pair by One
DCX
Decrement Register Pair by One
Logical Group
ACI
Add Immediate data to Accumulator Using Carry
SUB
Subtract from Accumulator
SUI Subtract
Immediate Data from Accumulator
SBB Subtract
from Accumulator Using Borrow (Carry) Flag
SBI Subtract
Immediate from Accumulator Using Borrow (Carry) Flag
INR
Increment Specified Byte by One
DCR
Decrement Specified Byte by One
INX
Increment Register Pair by One
DCX
Decrement Register Pair by One
Branch
group
- The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as follows:
- JMP Jump
- CALL Call
- RET Return
- Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows:
- NZ Not Zero (Z = 0)
- Z Zero (Z = 1)
- NC No Carry (C = 0)
- C Carry (C = 1)
- PO Parity Odd (P = 0)
- PE Parity Even (P = 1)
- P Plus (S = 0)
- M Minus (S = 1)
Q.
What is assembler Directive?
- Assembler directive
- Directives are a way to give information to the assembler.
- An assembler directive is a message to the assembler that tells the assembler something it needs to know in order to carry out the assembly process;
8085
BLOCK DIAGRAM;
Q.
What is BUS AND CPU (processor)
Bus:
A shared group of wires used
for communicating signals among
devices
•
ADDRES BUS: the device
and the location within the device that
is being accessed
•
DATA
BUS: the data value being communicated
•
CONTROL
BUS: describes the action on the address
and data buses
•
CPU: Core of the
processor, where instructions are executed
•
( High-level language: a = b + c
•
Assembly language: add r1 r2 r3
•
Machine language: 0001001010111010101
)
Q.
Draw and define bus stracture of 8085 ?
The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with
the other units using a 16-bit address bus, an 8-bit data bus and a control
bus.
Address Bus
- Consists of 16 address lines: A0 – A15
- Operates in unidirectional mode: The address bits are always sent from the MPU to peripheral devices, not reverse.
- 16 address lines are capable of addressing a
total of 216
= 65,536 (64k) memory locations.
- Address locations: 0000 (hex) – FFFF (hex)
Data Bus
- Consists of 8 data lines: D0 – D7
- Operates in bidirectional mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.
- Data range: 00 (hex) – FF (hex)
•
Control Bus
•
Consists of
various lines carrying the control signals
such as read / write enable, flag bits.
Q.
Draw and define the 8085 registers ?
Registers
- Six general purpose 8-bit registers: B, C, D, E, H, L
- They can also be combined as register pairs to
perform
16-bit operations: BC, DE, HL
- Registers are programmable (data load, move, etc.)
- Accumulator
- Single 8-bit register that is part of the ALU !
- Used for arithmetic / logic operations – the result is always stored in the accumulator
Flag Bits
- Indicate the result of condition tests.
- Carry, Zero, Sign, Parity, etc.
- Conditional operations (IF / THEN) are executed based on the condition of these flag bits.
Program Counter (PC)
Contains the
memory address (16 bits) of the instruction
that will be executed in the next step.
Stack
Pointer (SP)
Q. What do you mean by 8085 internal
architecture ?
The internal architecture of the 8085 CPU
is capable of performing the following
operations:
- Store 8-bit data (Registers, Accumulator)
- Perform arithmetic and logic operations (ALU)
- Test for conditions (IF / THEN)
- Sequence the execution of instructions Store temporary data in RAM during execution
Q. Draw the
pin diagram of 8085 .
8085 pin
diagram
|
_________
_________
|
|
_|
\__/
|_
|
|
--> X1 |_|1
40|_|
Vcc (+5V) |
|
_|
|_
|
|
--> X2
|_|2
39|_| HOLD <-- |
|
_|
|_
|
|
<-- RESET OUT |_|3
38|_|
HLDA --> |
|
_|
|_
|
|
<-- SOD
|_|4
37|_| CLK (OUT) --> |
|
_|
|_ ________ |
|
--> SID
|_|5
36|_| RESET IN <-- |
|
_|
|_
|
|
--> TRAP
|_|6
35|_| READY <-- |
|
_|
|_
_ |
|
--> RST 7.5
|_|7
34|_| IO/M --> |
|
_|
|_
|
|
--> RST 6.5
|_|8
33|_| S1 --> |
|
_|
|_ __
|
|
--> RST 5.5
|_|9
32|_| RD --> |
|
_|
|_
__
|
|
--> INTR |_|10
8085A 31|_| WR
--> |
|
____
_|
|_
|
|
<-- INTA
|_|11
30|_| ALE --> |
|
_|
|_
|
|
<--> AD0
|_|12
29|_| S0 --> |
|
_|
|_
|
|
<--> AD1
|_|13
28|_| A15 --> |
|
_|
|_
|
|
<--> AD2
|_|14
27|_| A14 --> |
|
_|
|_
|
|
<--> AD3
|_|15
26|_| A13 --> |
|
_|
|_
|
|
<--> AD4
|_|16
25|_| A12 --> |
|
_|
|_
|
|
<--> AD5
|_|17
24|_| A11 --> |
|
_|
|_
|
|
<--> AD6
|_|18
23|_| A10 --> |
|
_|
|_
|
|
<--> AD7
|_|19
22|_| A9 --> |
|
_|
|_
|
|
(Gnd) Vss
|_|20
21|_| A8 --> |
|
|______________________|
|
|
|
|
|
8086
|
FOR CONVINIRNT STUDY
OF MICROPROCESSORS TWO TYPES OF MODELS ARE USED
Ø
PROGRAMMER’S
MODEL :- THIS MODEL SHOWS FEATURES , SUCH AS INTERNAL REGISTERS, ADDRESS ,DATA
& CONTROL BUSES ; THAT WE NEED TO PROGRAM THE DEVICE.
Ø
THE
HARDWARE MODEL:- THIS MODEL SHOWS THE PIN DIAGRAM AND THE SIGNALS TO/FROM THIS PINS TO
UNDERSTAND HOW A MOCROCOMPUTER SYSTEM IS BUILT AROUND.
Q. What do you mean by
8086 bus stracture ?
THE 8086 HAS
q
20
ADDRESS LINES
q 20 address
lines so a 220 byte address space
q Pins A0-A19
provide the address
q For 8086,
A0-A15 appear multiplexed with D0-D15 to form AD0-AD15
q For 8088,
A0-A7 appear multiplexed with D0-D7 to form AD0-AD7
q
q
16
DATA LINES
q For 8086, 16
bit data bus D0-D15 (multiplexed as AD0-AD15)
q For 8088, 8
bit data bus D0-D7 (multiplexed as AD0-AD7)
q 8086 may use
only D0-D7 or D8-D15 if appropriate
q
4-10 CONTROL LINES
•
Control Bus
–
For memory access, the following pins are used:
RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE
WITH THIS THE 8086 IS
ABLE
q
TO ADDRESS 1,048,,576 (220 ) MEMORY
LOCATIONS/PORTS.
q
TO MANIPULATE AND/OR OPERATE ON 16-BITS(2-BYTES) OF
DATA AT A TIME.
TO GENERATE NECESSARY CONTROL SIGNALS.
Q.Draw and define the architecture of 8086 .
THE INTERNAL ARCHITECTURE OF 8086 CAN BE MAINLY DIVIDED INTO TWO UNITS:
q BUS INTERFACE UNIT (BIU)
EXECUTION UNIT (EU)
THE BIU CONTAINS :
q IP - the
Instruction Pointer
q CS - the Code
Segment Register
q DS - the Data Segment
Register
q SS - the Stack
Segment Register
q ES - the Extra Segment Register
q INSTRUCTION
POINTER (IP)
THE EU CONTAINS THE
FOLLOWING 8-BIT REGISTERS:
q AH & AL
(AX-16 BIT)
q BH & BL
(BX-16 BIT)
q CH & CL
(CX-16 BIT)
q DH 7 DL (DX-16
BIT)
IT ALSO INCLUDES THE FOLLOWING
16-BIT REGISTERS:
q STACK POINTER
(SP)
q BASE POINTER
(BP)
q SOURCE INDEX
(SI)
DESTINATION INDEX (DI)
Q. what do you mean
8086 PHYSICAL MEMORY?
THE TOTAL MEMORY (1MB) OF 8086 IS ARRANGED IN TWO BANKS. AN ODD BANK AND
AN EVEN BANK. BOTH THE BANKS HAVE EQUAL NO. OF LOCATIONS.
THE ODD BANK CONTAINS ODD NUMBERED MEM. LOCATIONS.IT IS KNOWN AS UPPER
BANK.
THE EVEN BANK CONTAINS ONLY EVEN NUMBERED MEM. LOCATIONS.IT IS KNOWN AS
LOWER BANK.
THIS ARRANGE MENT IS DONE IN ORDER TO SPEED UP THE OPERATION.
THE ARRANGEMENT AND THE SIGNAL FOLLOWED, EXPLAINS THE SAME.
Q. Draw the 8086 Block
Diagram.
Q. What do mean of addressing mode ?
The addressing mode means where and how the CPU gets the operands when
the instruction is executed.
•
Immediate Addressing Mode
---CPU gets the operand
from the instruction
•
Register Addressing Mode
---CPU gets the operand
from one of the internal registers
•
Memory Addressing Mode
---CPU gets the operand
from the memory location(s)
Q. Define the registers of 8086
•
16-bit Segment Registers:
CS, DS, ES, SS
•
8-bit data Registers:
AH, AL, BH, BL, CH, CL, DH, DL
•
16-bit data Registers:
AX, BX, CX, DX, SI, DI, BP, SP
•
16-bit Address registers:
SI, DI, BP, BX
•
Only BX out of AX, BX, CX, DX
can be used as Address register
•
•
FLAGS REGISTERS:
•
Flag is a bit of special
information
•
9 Flags
•
6 Status Flags
•
Cy, Ac, S, Z, P, Overflow
•
3 Control flags
•
IE, T, D
•
•
Q.WHAT do you mean by memory and memory
interfacing ?
•
semiconductor
memories are used as primary storage for data and code.
•
connected
to the CPU which asks for information (code or data)
•
Among
the most widely used are RAM and ROM
•
Memory
Capacity: The number of bits that a semiconductor memory chip can store
•
Memory
Organization
– Each memory chip
contains 2x locations where x is the number of address pins on the
chip
– Each location
contains y bits, where y is the number of data pins on the chip
– The entire chip will
contain 2x * y bits
– Ex. Memory
organization of 4K x 4: 212 = 4096 locations, each location holding 4 bits
• Memory Speed (access
time)
•
ROM
(Read Only Memory)
–
ROM
is the type of memory that does not lose its contents when power is turned off.
It is also called nonvolatile memory.
•
PROM
(Programmable Memory)
–
User
programmable (one-time programmable) memory
–
If
the information burned into PROM is wrong, it needs to be discarded since
internal fuses are blown permanently.
–
Special
equipment needed: ROM burner or ROM programmer
•
EPROM
(Erasable Programmable ROM) 2,000 times
–
Allows
making changes in the contents of PROM after it is burned
–
One
can program the memory chip and erase it thousands of times
–
Erasing
its contents can take up to 20 minutes; the entire chip is erased
–
All
EPROM chips have a window that is used to shine ultraviolet (UV) radiation to
erase its contents
–
Also
referred to as UV-EPROM
–
EEPROM (Electrically Erasable ROM) 500,000
times
–
Method of erasure is electrical
–
Moreover,
one can select which byte to be erased
–
Cost
per bit is much higher than for UV-EPROM
–
Flash Memory EPROM
–
First, the process of erasure of the entire
contents takes less than a second, or one might say in a flash, hence its name:
flash memory
–
When flash memory’s contents are erased, the
entire device is erased.
–
Even
though flash memories are writeable, like EPROMs they find their widest use in
microcomputer systems for storage of firmware
–
RAM (Random Access Memory) infinite times
–
RAM memory is called volatile memory since
cutting off the power to the IC will mean the loss of data.
Also referred to as R/WM
(Read And Write)unit 2
Intel 8086 CPU: An Introduction
8086 Features
•
16-bit Arithmetic Logic Unit
• 16-bit data bus
• 20-bit address bus - 220 =
1,048,576 = 1 meg
The
address refers to a byte in memory. In the 8086,
bytes at even addresses come in on the low
half of the
data bus (bits 0-7) and bytes at odd addresses come in
on the upper
half of the data bus (bits 8-15).
The
8086 can read a 16-bit word at an even address in
one operation and at an odd
address in two operations.
The
least significant byte of a word on an 8086 family
microprocessor is at the
lower address.
8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and
the
Execution Unit (EU).
• The BIU fetches instructions, reads and writes data, and
computes the
20-bit address.
• The EU decodes and executes the instructions using the
16-bit ALU.
• The BIU contains the following registers:
IP - the
Instruction Pointer
CS - the
Code Segment Register
DS - the
Data Segment Register
SS - the
Stack Segment Register
ES - the
Extra Segment Register
The BIU fetches instructions using the CS and IP, written CS:IP, to construct
the 20-bit address. Data is fetched using
a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode.
